Semiconductor interconnect structure

In a semiconductor device, an interlevel insulating film formed between a Cu interconnection, formed by damascene, and an upper metal interconnection layer on it has a multilayered structure made up of a Cu diffusion preventive insulating layer and another insulating film. The Cu diffusion preventiv...

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Bibliographische Detailangaben
Hauptverfasser:	OHTO KOICHI, MATSUI TAKAYUKI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CHEMICAL SURFACE TREATMENT CHEMISTRY COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING MATERIAL WITH METALLIC MATERIAL COATING METALLIC MATERIAL DIFFUSION TREATMENT OF METALLIC MATERIAL ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL METALLURGY SEMICONDUCTOR DEVICES SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION
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Beschreibung
Zusammenfassung:	In a semiconductor device, an interlevel insulating film formed between a Cu interconnection, formed by damascene, and an upper metal interconnection layer on it has a multilayered structure made up of a Cu diffusion preventive insulating layer and another insulating film. The Cu diffusion preventive insulating layer has a multilayered structure made up of not less than two layers. A method for manufacturing the semiconductor device is also disclosed.