Elevated source drain disposable spacer CMOS

In one embodiment of the invention, source and drain regions are formed as well as source and drain contact regions. Thereafter source and drain extension regions are formed. In another embodiment, elevated source and drain regions are formed as well as source and drain extension regions. Thereafter...

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Bibliographische Detailangaben
Hauptverfasser:	ROY RONNEN A, LAVOIE CHRISTIAN, LEE KAM-LEUNG, CABRAL, JR. CYRIL
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS
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Beschreibung
Zusammenfassung:	In one embodiment of the invention, source and drain regions are formed as well as source and drain contact regions. Thereafter source and drain extension regions are formed. In another embodiment, elevated source and drain regions are formed as well as source and drain extension regions. Thereafter source and drain contact regions are formed at a temperature up to about 600° C. and an annealing time of up to about one minute.