Mask network design for scan-based integrated circuits

A method and apparatus for selectively masking off unknown ('x') captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221 , a plurality of pattern generators 208 , a plurality of pattern compactors 213 , with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222 , or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.