Semiconductor memory device using VSS or VDD bit line precharge approach without reference cell

Provided is a semiconductor memory device using a VSS or VDD bit line precharge approach without a reference cell. Two P-type sense amplifiers are used in the VSS precharge approach and two N-type sense amplifiers are used in the VDD precharge approach. In one of the two sense amplifiers, a transistor that drives a bit line has a lower current driving capability than that of the other transistor that drives a complementary bit line. In the other of the two sense amplifiers, a transistor that drives the complementary bit line has a lower current driving capability than that of the other transistor that drives the bit line. Accordingly, one of the two sense amplifiers first operates and the other of the two sense amplifiers operates after a predetermined delay time according to a position of one of two memory cells, which is selected when a word line is enabled, so as to properly sense data "0" and "1", thereby solving the problems of the conventional VSS or VDD precharge approach using the reference cell.