Semiconductor component and method for precluding stress-induced void formation in the semiconductor component

Semiconductor component and method for precluding stress-induced void formation in the semiconductor component

A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A metallization...

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Hauptverfasser: MARATHE AMIT, HAU-RIEGE CHRISTINE, SANCHEZ, JR. JOHN
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator MARATHE AMIT
HAU-RIEGE CHRISTINE
SANCHEZ, JR. JOHN
description A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A metallization system is formed over the layer of dielectric material, wherein the metallization system includes a portion having gaps or apertures which inhibit stress induced void formation.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7026225B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7026225B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7026225B13</originalsourceid><addsrcrecordid>eNqNjLsOwjAMRbswIOAf_AOVIAjYi0DshbmKEpdaauwodvl-HmJkYDrDPffMK24xURCOUzApECRlYWQDzxES2iAR-teQC4ZxisR3UCuoWtP7gxEeQh8leSNhIAYbEPR3dlnNej8qrr5cVHA-XY-XGrN0qNkHZLTu1h7Wbu_crtls_1Ce5t5Dhw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor component and method for precluding stress-induced void formation in the semiconductor component</title><source>esp@cenet</source><creator>MARATHE AMIT ; HAU-RIEGE CHRISTINE ; SANCHEZ, JR. JOHN</creator><creatorcontrib>MARATHE AMIT ; HAU-RIEGE CHRISTINE ; SANCHEZ, JR. JOHN</creatorcontrib><description>A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A metallization system is formed over the layer of dielectric material, wherein the metallization system includes a portion having gaps or apertures which inhibit stress induced void formation.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060411&amp;DB=EPODOC&amp;CC=US&amp;NR=7026225B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060411&amp;DB=EPODOC&amp;CC=US&amp;NR=7026225B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MARATHE AMIT</creatorcontrib><creatorcontrib>HAU-RIEGE CHRISTINE</creatorcontrib><creatorcontrib>SANCHEZ, JR. JOHN</creatorcontrib><title>Semiconductor component and method for precluding stress-induced void formation in the semiconductor component</title><description>A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A metallization system is formed over the layer of dielectric material, wherein the metallization system includes a portion having gaps or apertures which inhibit stress induced void formation.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLsOwjAMRbswIOAf_AOVIAjYi0DshbmKEpdaauwodvl-HmJkYDrDPffMK24xURCOUzApECRlYWQDzxES2iAR-teQC4ZxisR3UCuoWtP7gxEeQh8leSNhIAYbEPR3dlnNej8qrr5cVHA-XY-XGrN0qNkHZLTu1h7Wbu_crtls_1Ce5t5Dhw</recordid><startdate>20060411</startdate><enddate>20060411</enddate><creator>MARATHE AMIT</creator><creator>HAU-RIEGE CHRISTINE</creator><creator>SANCHEZ, JR. JOHN</creator><scope>EVB</scope></search><sort><creationdate>20060411</creationdate><title>Semiconductor component and method for precluding stress-induced void formation in the semiconductor component</title><author>MARATHE AMIT ; HAU-RIEGE CHRISTINE ; SANCHEZ, JR. JOHN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7026225B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MARATHE AMIT</creatorcontrib><creatorcontrib>HAU-RIEGE CHRISTINE</creatorcontrib><creatorcontrib>SANCHEZ, JR. JOHN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MARATHE AMIT</au><au>HAU-RIEGE CHRISTINE</au><au>SANCHEZ, JR. JOHN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor component and method for precluding stress-induced void formation in the semiconductor component</title><date>2006-04-11</date><risdate>2006</risdate><abstract>A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A metallization system is formed over the layer of dielectric material, wherein the metallization system includes a portion having gaps or apertures which inhibit stress induced void formation.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor component and method for precluding stress-induced void formation in the semiconductor component
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-17T07%3A51%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MARATHE%20AMIT&rft.date=2006-04-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7026225B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true