Concurrent electrical signal wiring optimization for an electronic package
The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, pro...
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creator | BUDELL TIMOTHY W AUDET JEAN BUFFET PATRICK H CARON ALAIN |
description | The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7017128B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7017128B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7017128B23</originalsourceid><addsrcrecordid>eNqNyrEKwkAMANBbHET9h_yAYOtQZ4sirupcQkiP4JkcuRPBr7dDP8DpLW8Zrr0pvd1ZK3Biqi6ECYpEnfiIi0awXOUlX6xiCqM5oM7ZVAgy0hMjr8NixFR4M7sKcD7d-8uWsw1cpsXKdXjcul3TNe3h2O7_KD8T8jVx</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Concurrent electrical signal wiring optimization for an electronic package</title><source>esp@cenet</source><creator>BUDELL TIMOTHY W ; AUDET JEAN ; BUFFET PATRICK H ; CARON ALAIN</creator><creatorcontrib>BUDELL TIMOTHY W ; AUDET JEAN ; BUFFET PATRICK H ; CARON ALAIN</creatorcontrib><description>The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PHYSICS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060321&DB=EPODOC&CC=US&NR=7017128B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060321&DB=EPODOC&CC=US&NR=7017128B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BUDELL TIMOTHY W</creatorcontrib><creatorcontrib>AUDET JEAN</creatorcontrib><creatorcontrib>BUFFET PATRICK H</creatorcontrib><creatorcontrib>CARON ALAIN</creatorcontrib><title>Concurrent electrical signal wiring optimization for an electronic package</title><description>The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PHYSICS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwkAMANBbHET9h_yAYOtQZ4sirupcQkiP4JkcuRPBr7dDP8DpLW8Zrr0pvd1ZK3Biqi6ECYpEnfiIi0awXOUlX6xiCqM5oM7ZVAgy0hMjr8NixFR4M7sKcD7d-8uWsw1cpsXKdXjcul3TNe3h2O7_KD8T8jVx</recordid><startdate>20060321</startdate><enddate>20060321</enddate><creator>BUDELL TIMOTHY W</creator><creator>AUDET JEAN</creator><creator>BUFFET PATRICK H</creator><creator>CARON ALAIN</creator><scope>EVB</scope></search><sort><creationdate>20060321</creationdate><title>Concurrent electrical signal wiring optimization for an electronic package</title><author>BUDELL TIMOTHY W ; AUDET JEAN ; BUFFET PATRICK H ; CARON ALAIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7017128B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PHYSICS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BUDELL TIMOTHY W</creatorcontrib><creatorcontrib>AUDET JEAN</creatorcontrib><creatorcontrib>BUFFET PATRICK H</creatorcontrib><creatorcontrib>CARON ALAIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BUDELL TIMOTHY W</au><au>AUDET JEAN</au><au>BUFFET PATRICK H</au><au>CARON ALAIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Concurrent electrical signal wiring optimization for an electronic package</title><date>2006-03-21</date><risdate>2006</risdate><abstract>The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS CALCULATING CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PHYSICS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
title | Concurrent electrical signal wiring optimization for an electronic package |
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