Critical dimension edge placement and slope enhancement with central pixel dose addition and modulated inner pixels

Systems and methods for gray scale lithography for defining edges such as on microelectronic device patterns during integrated circuit fabrication are disclosed. Methods for critical dimension edge placement and slope enhancement utilize central pixel dose addition or modulated inner pixels. A method for gray scale lithography for defining edges of features generally comprises identifying a center pixel of a feature, exposing the general width of the feature including the identified center pixel with full doses, and enhancing the identified center pixel by exposing the identified center pixel with additional dose to accurately place the edge of the feature, whereby the edge of the feature is defined and moved by exposing the center pixel with the additional dose. Another method for gray scale lithography generally comprises identifying a proximal interior pixel immediately interior to an unbiased edge of the feature, exposing the general width of the feature full dosages, and exposing the proximal interior pixel with a dosage of elevated intensity selected from a set of gray levels, the elevated intensities being above the full dosage, the set of gray levels biases the edge of the feature and facilitates in further moving the edge of the feature in fractional increments of a pixel depending upon the gray level selected.