Methods for shielding one or more circuit of a printed circuit board

Methods for forming a metal shield on a printed circuit board ( 10 ) include depositing a first layer of metal ( 41 ) on a substrate ( 22 ) of the printed circuit board ( 10 ), depositing a first layer of dielectric material ( 42 ) on the first layer of metal ( 41 ), printing one or more circuits (...

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Hauptverfasser: BARRETO JOAQUIN, ARLEDGE JOHN K, SWIRBEL THOMAS J, UNDERWOOD JEFFREY A
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creator BARRETO JOAQUIN
ARLEDGE JOHN K
SWIRBEL THOMAS J
UNDERWOOD JEFFREY A
description Methods for forming a metal shield on a printed circuit board ( 10 ) include depositing a first layer of metal ( 41 ) on a substrate ( 22 ) of the printed circuit board ( 10 ), depositing a first layer of dielectric material ( 42 ) on the first layer of metal ( 41 ), printing one or more circuits ( 21, 21' ) on the first dielectric layer ( 42 ), depositing a second layer of dielectric material ( 43 ) over the one or more printed circuits ( 21, 21' ), forming a trench-like opening ( 44 ) in the two layers of dielectric material ( 42, 43 ) surrounding the one or more printed circuits ( 21, 21' ) so that the metal of the first layer ( 41 ) is exposed by the trench-like opening ( 44 ), depositing a second layer of metal ( 27 ) on the second layer of dielectric material ( 43 ) such that the second layer of metal ( 27 ) plates the trench-like opening ( 44 ) and makes electrical contact with the first metal layer ( 41 ).
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6990734B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6990734B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6990734B23</originalsourceid><addsrcrecordid>eNrjZHDxTS3JyE8pVkjLL1IozshMzUnJzEtXyM9LVQAK5OYXpSokZxYll2aWKOSnKSQqFBRl5pWkpsAFk_ITi1J4GFjTEnOKU3mhNDeDgptriLOHbmpBfnxqcUFicmpeakl8aLCZpaWBubGJk5ExEUoAH7syKw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Methods for shielding one or more circuit of a printed circuit board</title><source>esp@cenet</source><creator>BARRETO JOAQUIN ; ARLEDGE JOHN K ; SWIRBEL THOMAS J ; UNDERWOOD JEFFREY A</creator><creatorcontrib>BARRETO JOAQUIN ; ARLEDGE JOHN K ; SWIRBEL THOMAS J ; UNDERWOOD JEFFREY A</creatorcontrib><description>Methods for forming a metal shield on a printed circuit board ( 10 ) include depositing a first layer of metal ( 41 ) on a substrate ( 22 ) of the printed circuit board ( 10 ), depositing a first layer of dielectric material ( 42 ) on the first layer of metal ( 41 ), printing one or more circuits ( 21, 21' ) on the first dielectric layer ( 42 ), depositing a second layer of dielectric material ( 43 ) over the one or more printed circuits ( 21, 21' ), forming a trench-like opening ( 44 ) in the two layers of dielectric material ( 42, 43 ) surrounding the one or more printed circuits ( 21, 21' ) so that the metal of the first layer ( 41 ) is exposed by the trench-like opening ( 44 ), depositing a second layer of metal ( 27 ) on the second layer of dielectric material ( 43 ) such that the second layer of metal ( 27 ) plates the trench-like opening ( 44 ) and makes electrical contact with the first metal layer ( 41 ).</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES ; TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ; TECHNICAL SUBJECTS COVERED BY FORMER USPC ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060131&amp;DB=EPODOC&amp;CC=US&amp;NR=6990734B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060131&amp;DB=EPODOC&amp;CC=US&amp;NR=6990734B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BARRETO JOAQUIN</creatorcontrib><creatorcontrib>ARLEDGE JOHN K</creatorcontrib><creatorcontrib>SWIRBEL THOMAS J</creatorcontrib><creatorcontrib>UNDERWOOD JEFFREY A</creatorcontrib><title>Methods for shielding one or more circuit of a printed circuit board</title><description>Methods for forming a metal shield on a printed circuit board ( 10 ) include depositing a first layer of metal ( 41 ) on a substrate ( 22 ) of the printed circuit board ( 10 ), depositing a first layer of dielectric material ( 42 ) on the first layer of metal ( 41 ), printing one or more circuits ( 21, 21' ) on the first dielectric layer ( 42 ), depositing a second layer of dielectric material ( 43 ) over the one or more printed circuits ( 21, 21' ), forming a trench-like opening ( 44 ) in the two layers of dielectric material ( 42, 43 ) surrounding the one or more printed circuits ( 21, 21' ) so that the metal of the first layer ( 41 ) is exposed by the trench-like opening ( 44 ), depositing a second layer of metal ( 27 ) on the second layer of dielectric material ( 43 ) such that the second layer of metal ( 27 ) plates the trench-like opening ( 44 ) and makes electrical contact with the first metal layer ( 41 ).</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</subject><subject>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDxTS3JyE8pVkjLL1IozshMzUnJzEtXyM9LVQAK5OYXpSokZxYll2aWKOSnKSQqFBRl5pWkpsAFk_ITi1J4GFjTEnOKU3mhNDeDgptriLOHbmpBfnxqcUFicmpeakl8aLCZpaWBubGJk5ExEUoAH7syKw</recordid><startdate>20060131</startdate><enddate>20060131</enddate><creator>BARRETO JOAQUIN</creator><creator>ARLEDGE JOHN K</creator><creator>SWIRBEL THOMAS J</creator><creator>UNDERWOOD JEFFREY A</creator><scope>EVB</scope></search><sort><creationdate>20060131</creationdate><title>Methods for shielding one or more circuit of a printed circuit board</title><author>BARRETO JOAQUIN ; ARLEDGE JOHN K ; SWIRBEL THOMAS J ; UNDERWOOD JEFFREY A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6990734B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</topic><topic>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</topic><toplevel>online_resources</toplevel><creatorcontrib>BARRETO JOAQUIN</creatorcontrib><creatorcontrib>ARLEDGE JOHN K</creatorcontrib><creatorcontrib>SWIRBEL THOMAS J</creatorcontrib><creatorcontrib>UNDERWOOD JEFFREY A</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BARRETO JOAQUIN</au><au>ARLEDGE JOHN K</au><au>SWIRBEL THOMAS J</au><au>UNDERWOOD JEFFREY A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Methods for shielding one or more circuit of a printed circuit board</title><date>2006-01-31</date><risdate>2006</risdate><abstract>Methods for forming a metal shield on a printed circuit board ( 10 ) include depositing a first layer of metal ( 41 ) on a substrate ( 22 ) of the printed circuit board ( 10 ), depositing a first layer of dielectric material ( 42 ) on the first layer of metal ( 41 ), printing one or more circuits ( 21, 21' ) on the first dielectric layer ( 42 ), depositing a second layer of dielectric material ( 43 ) over the one or more printed circuits ( 21, 21' ), forming a trench-like opening ( 44 ) in the two layers of dielectric material ( 42, 43 ) surrounding the one or more printed circuits ( 21, 21' ) so that the metal of the first layer ( 41 ) is exposed by the trench-like opening ( 44 ), depositing a second layer of metal ( 27 ) on the second layer of dielectric material ( 43 ) such that the second layer of metal ( 27 ) plates the trench-like opening ( 44 ) and makes electrical contact with the first metal layer ( 41 ).</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
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language eng
recordid cdi_epo_espacenet_US6990734B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
TECHNICAL SUBJECTS COVERED BY FORMER USPC
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
title Methods for shielding one or more circuit of a printed circuit board
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T19%3A23%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BARRETO%20JOAQUIN&rft.date=2006-01-31&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6990734B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true