System and method for synchronizing divide-by counters

A synchronization system capable of simultaneously resetting frequency divide-by counters ( 124 A , 124 B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal ( 168 A , 168 B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit ( 176 A , 176 B) for each processor that simulates in the undivided signal (Mclk/1 signal ( 136 A , 136 B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal ( 172 A , 172 B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal ( 112 ) and sends an asynchronous offset signal ( 194 A , 194 B) to a counter re-setter ( 196 A , 196 B) that resets the divide-by counter to zero based on the offset signal.