No-precharge FAMOS cell and latch circuit in a memory device

No-precharge FAMOS cell and latch circuit in a memory device

The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The read circuit includes circuitry that reduces the drive strength of the fuse. A transmission gate couples the read circuit to the latch circuit...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: IMONDI GIULIANO GENNARO
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The read circuit includes circuitry that reduces the drive strength of the fuse. A transmission gate couples the read circuit to the latch circuit. The transmission gate isolates the fuse from the latch. When a reset condition occurs, the data that was in latch circuit remains after the reset condition is complete.