Register for the parallel-serial conversion of data
Register for the parallel-serial conversion of data having a plurality of cyclically driven shift registers ( 2 ), each comprising series-connected data holding elements ( 3 ), each data holding element ( 3 ) being connected to a data input line ( 5 ), each shift register ( 2 ), upon receiving an in...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | Register for the parallel-serial conversion of data having a plurality of cyclically driven shift registers ( 2 ), each comprising series-connected data holding elements ( 3 ), each data holding element ( 3 ) being connected to a data input line ( 5 ), each shift register ( 2 ), upon receiving an input control signal (INP) for the shift register ( 2 ), loading the data present on the data input lines ( 5 ) into the data holding elements ( 3 ) connected thereto; each shift register ( 2 ), upon receiving an output control signal (OUTP) for the shift register ( 2 ), outputting the datum buffer-stored in the last data holding element of the shift register ( 2 ), in which case there is connected downstream of each shift register ( 2 ) a further data holding element ( 10 ), which, upon receiving an input control signal (INP) for loading the preceding shift register ( 2 ), is preloaded with the datum for the first data holding element ( 3 - 3 ) of the shift register ( 2 ) and, upon reception of the output control signal (OUTP) for the shift register ( 2 ), outputs said preloaded datum to an output data line ( 22 ) via a data signal driver ( 18 ) for generating a serial output data stream with unambiguous data signal states. |
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