Burst transfer memory

The present invention provides a burst transfer memory comprising a first memory having a cell array arranged in a matrix, a second memory which has a cell array arranged in a matrix and which performs a random access operation at a higher speed than the first memory, and an interface circuit which...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KOINUMA HIROYUKI, TAKAHASHI MAKOTO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:The present invention provides a burst transfer memory comprising a first memory having a cell array arranged in a matrix, a second memory which has a cell array arranged in a matrix and which performs a random access operation at a higher speed than the first memory, and an interface circuit which controls the first and second memories as one burst transfer memory, and wherein the interface circuit allocates addresses to the first and second memories as consecutive addresses, and the interface circuit substantially simultaneously starts the first random access to the first and second memories, accesses the second memory before a word line of the first memory is activated, and consecutively accesses a page of the first memory after the word line of the first memory has been activated.