Contrast adjusting circuit

A contrast adjusting circuit used in a PDP display prevents the image from being whitish by suppressing the rise of the luminance at a low level when the contrast is heightened and optimally adjusts the contrast of the images always varying with time. The circuit contains an average luminance calcul...

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1. Verfasser: BANNAI MASAYUKI
Format: Patent
Sprache:eng
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Zusammenfassung:A contrast adjusting circuit used in a PDP display prevents the image from being whitish by suppressing the rise of the luminance at a low level when the contrast is heightened and optimally adjusts the contrast of the images always varying with time. The circuit contains an average luminance calculating section ( 12 ), an LUT ( 14 ), and an output video data calculating section ( 16 ), wherein the average luminance calculating section ( 12 ) determines the average luminance level APL for n frame images from the input video data X (X>=0) on the X-Y coordinate system, the LUT ( 14 ) determines central value data Xc, Yc from the APL, and the output video data calculating section ( 16 ) determines the output video data Y (Y>=0) collected after the contrast is adjusted according to the calculation formula Y=A.X+Yc-A.Xc where A (A>0) is the slope variably set for contrast adjustment, whereby the rise of the luminance at a low level when A is increased and the contrast is heightened, is suppressed to adjust the contrast corresponding to the APL for frame images.