Phase locked loop circuit having wide locked range and semiconductor integrated circuit device having the same

Provided are a phase locked loop (PLL) circuit having a wide locked range and a semiconductor integrated circuit (IC) device having the PLL circuit. The provided PLL circuit includes a phase/frequency detector for detecting a phase difference between an external input signal and an output signal of the PLL circuit; a charge pump for increasing or decreasing an output voltage level in response to the output signal of the phase/frequency detector; a loop filter for removing a high frequency element from the output voltage of the charge pump; a voltage controlled oscillation unit for outputting a signal having a predetermined frequency as an output signal of the PLL circuit in response to the output voltage of the loop filter; and a voltage controlled oscillator (VCO) range shift unit for decreasing a sensitivity of the output signal of the PLL circuit to the output voltage of the loop filter by increasing or decreasing an internal current of the voltage controlled oscillation unit in response to the output voltage of the loop filter. Accordingly, a jitter generated in the output signal of the PLL circuit decreases even when a noise voltage is input to the output voltage of the loop filter.