DMA scheduling mechanism
A DMA scheduling mechanism for transmission of fragmented buffers having a processor for controlling several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. The system handles transmission of network packets which are reas...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A DMA scheduling mechanism for transmission of fragmented buffers having a processor for controlling several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. The system handles transmission of network packets which are reassembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor. |
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