Memory interface for reading/writing data from/to a memory

A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associate...

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Bibliographische Detailangaben
Hauptverfasser:	DEWAR KEVIN DOUGLAS, ROBBINS WILLIAM PHILIP, BARNES MARK, KULIGOWSKI ANDREW PETER, FINCH HELEN ROSEMARY, SMITH COLIN, PATTERSON DONALD W. WALKER, BIRCH NICHOLAS, SOTHERAN MARTIN WILLIAM, BARNES DAVID ANDREW, WISE ADRIAN P, JONES ANTHONY MARK, CLAYDON ANTHONY PETER J
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING CODE CONVERSION IN GENERAL CODING COMPUTING COUNTING DECODING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY IMAGE DATA PROCESSING OR GENERATION, IN GENERAL INFORMATION STORAGE INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER PHYSICS PICTORIAL COMMUNICATION, e.g. TELEVISION TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.