Apparatus for stopping and starting a clock in a clock forwarded I/O system depending on the presence of valid data in a receive buffer

An efficient clock start and stop apparatus for clock forwarded system I/O. The apparatus may include a buffer coupled to receive incoming data from a data source. The buffer is clocked by a first clock signal that is provided by the data source. The buffer is configured to store the incoming data in a plurality of sequential lines in response to the first clock signal. The buffer may be further configured to store a plurality of bits in a plurality of occupied-bit registers. Each one of the plurality of occupied-bit registers indicates that data is present in a corresponding sequential line in the buffer. The apparatus may further include a clock gate circuit coupled to the buffer and configured to provide a second clock signal. The clock gate circuit may be further configured to start the second clock signal when valid data is present in the buffer and to stop the second clock signal when no data is present in the buffer.