Method and apparatus for managing out of order memory transactions

Method and apparatus for managing out of order memory transactions

According to one embodiment, a computer system is disclosed. The computer system comprises a main memory; and a chip set coupled to the main memory. The chip set comprises a transaction memory, a first bank controller and a second bank controller coupled to the transaction memory. The first bank con...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: MANSEAU DANIEL A
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:According to one embodiment, a computer system is disclosed. The computer system comprises a main memory; and a chip set coupled to the main memory. The chip set comprises a transaction memory, a first bank controller and a second bank controller coupled to the transaction memory. The first bank controller stores transaction data to be transmitted to a first bank of main memory within the transaction memory according to a first linked list. The second bank controller stores transaction data to be transmitted to a second bank of main memory within the transaction memory according to a second linked list.