Memory array
An object of the invention is to obtain a memory array capable of preventing coupling noise from being produced on a cell plate voltage line. A memory array of the invention comprises: first and second dummy word lines (DWL0 and DWL1); a first dummy memory cell (DMC0) connected to a first bit line (...
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| creator | KAIHATSU MINORU |
| description | An object of the invention is to obtain a memory array capable of preventing coupling noise from being produced on a cell plate voltage line. A memory array of the invention comprises: first and second dummy word lines (DWL0 and DWL1); a first dummy memory cell (DMC0) connected to a first bit line (BL), the first dummy word line (DWL0) and a common cell plate voltage line (VL); and a second dummy memory cell (DMC1) connected to a second bit line (BLB), the second dummy word line (DWL1) and the voltage line (VL), wherein second dummy data having opposite polarity to polarity of first data are written in the second dummy memory cell (DMC1) so as to write the first data in a first memory cell (MC0), and first dummy data having opposite polarity to polarity of second data are written in the first dummy memory cell (DMC0) so as to write the second data in a second memory cell (MC1). |
| format | Patent |
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A memory array of the invention comprises: first and second dummy word lines (DWL0 and DWL1); a first dummy memory cell (DMC0) connected to a first bit line (BL), the first dummy word line (DWL0) and a common cell plate voltage line (VL); and a second dummy memory cell (DMC1) connected to a second bit line (BLB), the second dummy word line (DWL1) and the voltage line (VL), wherein second dummy data having opposite polarity to polarity of first data are written in the second dummy memory cell (DMC1) so as to write the first data in a first memory cell (MC0), and first dummy data having opposite polarity to polarity of second data are written in the first dummy memory cell (DMC0) so as to write the second data in a second memory cell (MC1).</description><edition>7</edition><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040727&DB=EPODOC&CC=US&NR=6768687B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040727&DB=EPODOC&CC=US&NR=6768687B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KAIHATSU MINORU</creatorcontrib><title>Memory array</title><description>An object of the invention is to obtain a memory array capable of preventing coupling noise from being produced on a cell plate voltage line. A memory array of the invention comprises: first and second dummy word lines (DWL0 and DWL1); a first dummy memory cell (DMC0) connected to a first bit line (BL), the first dummy word line (DWL0) and a common cell plate voltage line (VL); and a second dummy memory cell (DMC1) connected to a second bit line (BLB), the second dummy word line (DWL1) and the voltage line (VL), wherein second dummy data having opposite polarity to polarity of first data are written in the second dummy memory cell (DMC1) so as to write the first data in a first memory cell (MC0), and first dummy data having opposite polarity to polarity of second data are written in the first dummy memory cell (DMC0) so as to write the second data in a second memory cell (MC1).</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZODxTc3NL6pUSCwqSqzkYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxocFm5mYWZhbmTkbGRCgBANqNHZ0</recordid><startdate>20040727</startdate><enddate>20040727</enddate><creator>KAIHATSU MINORU</creator><scope>EVB</scope></search><sort><creationdate>20040727</creationdate><title>Memory array</title><author>KAIHATSU MINORU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6768687B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>KAIHATSU MINORU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KAIHATSU MINORU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Memory array</title><date>2004-07-27</date><risdate>2004</risdate><abstract>An object of the invention is to obtain a memory array capable of preventing coupling noise from being produced on a cell plate voltage line. A memory array of the invention comprises: first and second dummy word lines (DWL0 and DWL1); a first dummy memory cell (DMC0) connected to a first bit line (BL), the first dummy word line (DWL0) and a common cell plate voltage line (VL); and a second dummy memory cell (DMC1) connected to a second bit line (BLB), the second dummy word line (DWL1) and the voltage line (VL), wherein second dummy data having opposite polarity to polarity of first data are written in the second dummy memory cell (DMC1) so as to write the first data in a first memory cell (MC0), and first dummy data having opposite polarity to polarity of second data are written in the first dummy memory cell (DMC0) so as to write the second data in a second memory cell (MC1).</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
| title | Memory array |
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