Semiconductor test apparatus

The invention provides a structure that does not employ complicated and large-scale control circuits or control memory, minimizes the circuits for real time processing, and allows the use of refresh memory. The invention provides a test clock (8-1) comprising a data processing apparatus (1-1) provided for each electrode pin of the measured device (11), a memory (2-1) that carries out reading and writing of the test pattern data and the like, a first-in-first-out element (4-1) that executes queue processing of the data read out from the memory, a delay circuit (5-1) that delays the output signal of the first-in-first-out element, and a measured device driver (6-1) that inputs into the electrode pin the output signal of the delay circuit, and in which the data processing apparatus (1-1) of adjacent test blocks are connected into a loop via the input-output circuit (3-1).