Clock generating circuit generating a plurality of clock signals

A clock generating circuit of a semiconductor integrated circuit device includes a plurality of stages of frequency-dividing circuits connected in series, of which a first stage receives a reference clock signal, each frequency-dividing circuit requiring no reset signal; and a plurality of buffers respectively transmitting a reference clock signal and output clock signals of the plurality of frequency-dividing circuits to an internal circuit of the semiconductor integrated circuit device. Therefore, a plurality of clock signals having different frequencies with aligned edges can be generated without the need for separately providing an external pin for inputting the reset signal or a circuit for generating the reset signal.