Asic system architecture including data aggregation technique

Asic system architecture including data aggregation technique

An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: BOYLAN SEAN, WALSH BRENDAN, DE PAOR DENISE, COBURN DEREK, CREEDON TADHG, JENNINGS KEVIN, LARDNER MIKE, HYLAND KEVIN J, HUGHES SUZANNE M, GAVIN VINCENT
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.