Programmable memory based control for generating optimal timing to access serial flash devices

In its many aspects and variations, a method for accessing a peripheral memory from a processor is provided. The method comprises first initiating the access. Information is then written from the processor to an operational register in a processor memory to enable the peripheral memory. The processor then processes parallel instructions for a predetermined time during which the access occurs. When the access is over, the processor reads the operational register to disable the peripheral memory. In other aspects, an apparatus programmed to perform this method and a program storage medium encoded with instructions that, when executed by a computer, perform the method are provided.