Balanced load memory and method of operation

A memory provides a sensing scheme that maintains impedance balance between the route that the data takes to the sense amplifier and the route the reference or references take to the sense amplifier. Each sub-array of the memory has an adjacent column decoder that couples data to a data line that is also adjacent to the sub-array and may be considered part of the column decoder. The data for the selected sub-array is routed to the sense amplifier via its adjacent data line. The reference that is part of the selected sub-array is coupled to the data line of a non-selected sub-array. Thus the reference, which in the case of a MRAM type memory is preferably in close proximity to the location of the selected data, traverses a route to the sense amplifier that is impedance balanced with respect to the route taken by the data.