Coarse tuning for fractional-N synthesizers
The present invention provides an efficient coarse tuning process for fractional-N synthesizers. In general, a divided reference signal and a divided controllable oscillator (CO) signal from the phase lock loop (PLL) of a synthesizer are each further divided by a common factor M to provide an averag...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | The present invention provides an efficient coarse tuning process for fractional-N synthesizers. In general, a divided reference signal and a divided controllable oscillator (CO) signal from the phase lock loop (PLL) of a synthesizer are each further divided by a common factor M to provide an average reference signal and an average CO signal, respectively. Averaging the divided CO signal reduces jitter caused by fractional-N division of the CO signal. The frequencies of the average CO signal and the average reference signal are compared and the result is used to select an appropriate tuning curve for operating the CO. |
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