Memory hole modification and mixed technique arrangements for maximizing cacheable memory space

Cache defining arrangements for maximizing cacheable memory space, including a mixed technique scheme using a bottom-up scheme defining a first non-memory-hole portion using mainly substantially additive blocks of cacheable space, and a top-down scheme defining a second non-memory-hole portion by de...

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Hauptverfasser: MEYERS, JR. RONALD P, SCHELLING TODD A
Format: Patent
Sprache:eng
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Zusammenfassung:Cache defining arrangements for maximizing cacheable memory space, including a mixed technique scheme using a bottom-up scheme defining a first non-memory-hole portion using mainly substantially additive blocks of cacheable space, and a top-down scheme defining a second non-memory-hole portion by defining an oversized block of cacheable space and using mainly substantially subtractive blocks of cacheable space.