Display device

An object is to eliminate the effect of jitter in a sampling clock to realize proper sampling of a video signal. An A/D converter (1) samples a video signal in synchronization with a sampling clock (VCLK) at a rate of a period which is ½ times the video period. The phase of the sampling clock (VCLK) is corrected in a phase correcting circuit (9). The sampled signals are held alternately as data (DL) and (DR) in two latches (14) (15). A data switching portion (16) selects output signals from one of the two latches (14) and (15). A calculating portion (21) calculates an absolute difference value (DeltaD) between the data (DL) and (DR) in each video period. A calculating portion (22) calculates a maximum value (Dmax) among the absolute difference values (DeltaD) in one frame. A phrase control portion (19) controls the phase correcting circuit (9) and the data switching portion (16) so that a video signal processing circuit (2) can receive sampled signals which are sampled signals which are sampled at a phase corresponding to the center of a rising transition which the maximum value (Dmax) makes as the phase varies.