Host bus adapter based scalable performance storage architecture

One embodiment of a storage controller is described including a controller memory, one or more central processing units (CPUs), and a host bus adapter all coupled to a controller bus. The one or more CPUs are configured to produce data routing information dependent upon a data transfer command which directs a transfer of data between a host computer and one or more storage devices. The host bus adapter includes a receive unit and a transmit unit adapted for coupling to a transmission medium. The host bus adapter receives the data routing information, and forwards data associated with the data transfer command from the receive unit to the transmit unit dependent upon the data routing information such that the data associated with the data transfer command is not conveyed upon the controller bus and is not stored within the controller memory. As a result, the data transfer mechanism does not rely upon availability of the controller bus and/or the one or more CPUs, allowing independent scalability of input/output operations per second (IOPS) and data transfer rate of a storage system including the storage controller. Embodiments of storage and computer systems including the storage controller are also described.