Distributed test architecture for multiport RAMs or other circuitry

Distributed test architecture for multiport RAMs or other circuitry

An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises a first built in self test (BIST) circuit configured to test the first circuit. The second circuit generally comprises a second BIST circuit configured to test the second circuit. The second circuit m...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: NARAYANA PIDUGU L, THAKUR SANGEETA, HAMADEH EMAD
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
STATIC STORES
TESTING
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Beschreibung
Zusammenfassung:An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises a first built in self test (BIST) circuit configured to test the first circuit. The second circuit generally comprises a second BIST circuit configured to test the second circuit. The second circuit may not be adjacent to the first circuit.