Low or no-force bump flattening structure and method

Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewin...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	PIERSON MARK V, TRIVEDI AJIT K
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS CLADDING OR PLATING BY SOLDERING OR WELDING CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MACHINE TOOLS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS METAL-WORKING NOT OTHERWISE PROVIDED FOR PERFORMING OPERATIONS PRINTED CIRCUITS SEMICONDUCTOR DEVICES SOLDERING OR UNSOLDERING TRANSPORTING WELDING WORKING BY LASER BEAM
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	PIERSON MARK V TRIVEDI AJIT K
description	Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewing after chip placement.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6674647B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6674647B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6674647B23</originalsourceid><addsrcrecordid>eNrjZDDxyS9XyC9SyMvXTcsvSk5VSCrNLVBIy0ksKUnNy8xLVyguKSpNLiktSlVIzEtRyE0tychP4WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBZmbmJmYm5k5GxkQoAQDN6yyO</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Low or no-force bump flattening structure and method</title><source>esp@cenet</source><creator>PIERSON MARK V ; TRIVEDI AJIT K</creator><creatorcontrib>PIERSON MARK V ; TRIVEDI AJIT K</creatorcontrib><description>Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewing after chip placement.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; CLADDING OR PLATING BY SOLDERING OR WELDING ; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MACHINE TOOLS ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; METAL-WORKING NOT OTHERWISE PROVIDED FOR ; PERFORMING OPERATIONS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES ; SOLDERING OR UNSOLDERING ; TRANSPORTING ; WELDING ; WORKING BY LASER BEAM</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040106&DB=EPODOC&CC=US&NR=6674647B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040106&DB=EPODOC&CC=US&NR=6674647B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PIERSON MARK V</creatorcontrib><creatorcontrib>TRIVEDI AJIT K</creatorcontrib><title>Low or no-force bump flattening structure and method</title><description>Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewing after chip placement.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>CLADDING OR PLATING BY SOLDERING OR WELDING</subject><subject>CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MACHINE TOOLS</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>METAL-WORKING NOT OTHERWISE PROVIDED FOR</subject><subject>PERFORMING OPERATIONS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>SOLDERING OR UNSOLDERING</subject><subject>TRANSPORTING</subject><subject>WELDING</subject><subject>WORKING BY LASER BEAM</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDxyS9XyC9SyMvXTcsvSk5VSCrNLVBIy0ksKUnNy8xLVyguKSpNLiktSlVIzEtRyE0tychP4WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBZmbmJmYm5k5GxkQoAQDN6yyO</recordid><startdate>20040106</startdate><enddate>20040106</enddate><creator>PIERSON MARK V</creator><creator>TRIVEDI AJIT K</creator><scope>EVB</scope></search><sort><creationdate>20040106</creationdate><title>Low or no-force bump flattening structure and method</title><author>PIERSON MARK V ; TRIVEDI AJIT K</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6674647B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>CLADDING OR PLATING BY SOLDERING OR WELDING</topic><topic>CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MACHINE TOOLS</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>METAL-WORKING NOT OTHERWISE PROVIDED FOR</topic><topic>PERFORMING OPERATIONS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>SOLDERING OR UNSOLDERING</topic><topic>TRANSPORTING</topic><topic>WELDING</topic><topic>WORKING BY LASER BEAM</topic><toplevel>online_resources</toplevel><creatorcontrib>PIERSON MARK V</creatorcontrib><creatorcontrib>TRIVEDI AJIT K</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PIERSON MARK V</au><au>TRIVEDI AJIT K</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Low or no-force bump flattening structure and method</title><date>2004-01-06</date><risdate>2004</risdate><abstract>Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewing after chip placement.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US6674647B2
source	esp@cenet
subjects	BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS CLADDING OR PLATING BY SOLDERING OR WELDING CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MACHINE TOOLS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS METAL-WORKING NOT OTHERWISE PROVIDED FOR PERFORMING OPERATIONS PRINTED CIRCUITS SEMICONDUCTOR DEVICES SOLDERING OR UNSOLDERING TRANSPORTING WELDING WORKING BY LASER BEAM
title	Low or no-force bump flattening structure and method
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-26T07%3A25%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PIERSON%20MARK%20V&rft.date=2004-01-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6674647B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true