Low or no-force bump flattening structure and method

Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewin...

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Bibliographische Detailangaben
Hauptverfasser:	PIERSON MARK V, TRIVEDI AJIT K
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS CLADDING OR PLATING BY SOLDERING OR WELDING CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MACHINE TOOLS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS METAL-WORKING NOT OTHERWISE PROVIDED FOR PERFORMING OPERATIONS PRINTED CIRCUITS SEMICONDUCTOR DEVICES SOLDERING OR UNSOLDERING TRANSPORTING WELDING WORKING BY LASER BEAM
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Beschreibung
Zusammenfassung:	Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewing after chip placement.