Memory system for accelerating graphics operations within an electronic device

The present invention relates to a system and method for accelerating graphics. The system includes a memory device for accelerating graphics operations within an electronic device. A memory controller is used for controlling pixel data transmitted to and from the memory device. A cache memory is electrically coupled to the memory and is dynamically configurable to a selected usable size to exchange an amount of pixel data having the selected usable size with the memory controller. The memory device may be an SDRAM. The cache memory may also comprise a plurality of usable memory areas or tiles.