Parallel test in asynchronous memory with single-ended output path

An asynchronous memory device includes parallel test circuitry configured to interface with a single-ended output data path of the memory device and, in some cases, to provide a measure of a slowest cell access time for the memory device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the memory device and to provide first output signals indicative of logic states of the plurality of cells; and second circuitry configured to receive the first output signals and to produce a second output signal indicative of the logic states of the first output signals therefrom. For example, the first circuitry and the second circuitry may be configured as a wired NAND and wired NOR combination. In some cases, one or more of the cells may be included within a redundant row or column of the memory device. The first circuitry may include one or more circuits, each including an input path from a first number of the plurality of cells and configured to provide at least one of the first output signals. The second circuitry may include logic circuitry configured to receive the first output signals and a control signal and to provide the second output signal. For example, the second circuitry may include an exclusive OR circuit coupled to receive the first output signals and to produce the second output signal.