JTAG-based software to perform cumulative array repair

Repairing arrays on a processor with an on chip built in self test engine on the processor is provided. A subset of the arrays is selected for testing. Data patterns are sent from the test engine to the subset of arrays at a plurality of operating parameters. A response is received at the test engine from the subset of arrays at the operating parameters. The received response is compared to an expected response using the test engine, wherein the processor controller determines if additional test failures were detected by the test engine for the subset of arrays with a plurality of JTAG based instructions. Code in the processor controller then determines the states that need to be scanned into the scannable latches to force the array control logic to choose additional spare wordlines and/or bitlines to repair the newly identified failures in addition to all previously defined repair actions.