Simple 4T static ram cell for low power CMOS applications

An SRAM memory cell device comprises wordline and bitline inputs for enabling read/write access to memory cell contents, and, a diffusion region for maintaining a voltage to preserve memory cell content when the cell is not being accessed. The device further comprises a transistor device having a gate input for receiving a wordline voltage to turn off the transistor device when not performing memory cell read/write access; and, a gate oxide layer formed under the transistor device gate exhibiting resistance property for leaking current therethrough when the wordline voltage is applied to the gate input and the transistor device is off. The diffusion region receives voltage derived from the wordline voltage applied to said gate input to enable retention of said memory cell content in the absence of applied bitline voltage to thereby reduce power consumption.