Storage circuit with data retention during power down

A storage circuit for an integrated circuit is configured to couple to a first power supply voltage (e.g. a Vdd power supply voltage used by other circuitry within the integrated circuit) in response to a deassertion of a hold signal and configured to couple to a second power supply in response to an assertion of the hold signal. The second power supply voltage may be the hold signal voltage or another power supply voltage separate from the Vdd power supply voltage. The hold signal may be asserted and the Vdd power supply voltage may be removed. Leakage current in circuits powered only by the Vdd power supply voltage may be eliminated, while the storage circuit may retain its stored value. A system including the integrated circuit and a method for managing power in the system.