Apparatus and method for a random access peripheral unit

In a data processing system, the ability to provide indirect addressing capability is implemented by providing a peripheral system having a first memory unit, second memory unit, and a control unit. In a first embodiment of the invention, a first address signal applied to the control unit accesses a first location in the first memory unit. The signal group stored in the first location is a first address signal group. The first signal group is used by the control unit to access a second location in the second memory unit. The access of the second location can be used to store a data signal group therein in a write operation or can be used to retrieve a data signal group therefrom in a read operation. In the second embodiment of the invention, the control unit includes a pointer unit responsive to a plurality of control address signal groups. The control address signal groups cause the storage or retrieval of data signal groups in a data register in the control unit. The address signal group in the address register can be stored therein by an associated processing unit. The control address signal groups also determine a next address in an address register. The control unit uses the address signal group in the address register to determine an address signal group in a first location in the first memory unit. The address signal group in the first location is used to access a second location in the second memory unit. This access of the second location permits data signal groups to be transferred from the data register in the control unit to the second location or data signal groups to be transferred from the second location to the data register.