Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers

Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers

A conductive via pattern (110) between the uppermost metal interconnect layer (Mn) and next underlying metal interconnect layer (Mn-1) in the bond pad areas strengthens the interlevel dielectric (ILD3) between metal layers (Mn and Mn-1). The conductive via layer (110) may, for example, comprise para...

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Bibliographische Detailangaben
Hauptverfasser: RINCON REYNALDO, SUNDARARAMAN VISWANATHAN, HOTCHKISS GREGORY B, EDWARDS DARVIN R, CHISHOLM MICHAEL F
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
LAYERED PRODUCTS
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
PERFORMING OPERATIONS
SEMICONDUCTOR DEVICES
TRANSPORTING
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Zusammenfassung:A conductive via pattern (110) between the uppermost metal interconnect layer (Mn) and next underlying metal interconnect layer (Mn-1) in the bond pad areas strengthens the interlevel dielectric (ILD3) between metal layers (Mn and Mn-1). The conductive via layer (110) may, for example, comprise parallel rails (114) or a grid of cross-hatch rails (116). By spreading the stress concentration laterally, the conductive via layer (110) inhibits micro-cracking from stress applied to the bond pad (112).