Integrated circuit having optimized gate coupling capacitance

The present invention is directed to an integrated circuit having an optimized gate coupling capacitance. The integrated circuit includes a substrate defining a trench therein. A first conductive layer has a portion which extends into the trench. The first conductive layer defines a channel fabricated by a blanket etching step. An insulative layer is adjacent the first conductive layer. A second conductive layer is adjacent the insulative layer. The present invention is further directed to a method of fabricating an integrated circuit. The method includes forming a trench in the substrate, filling the trench with a trench fill material, etching the trench fill material until an upper surface of the trench fill material is below an upper surface of the substrate, providing a first conductive layer over at least a portion of the trench fill material, and blanket etching the first conductive layer until the portion is exposed.