Selective PCB via location to enhance cooling
Disclosed is a printed circuit board (PCB) layout for increasing the ability of the PCB to transfer heat away from a component mounted thereon. The locations of signal vias in the PCB are selected so as to define continuous pathways in a PCB heat sink layer. This allows heat to be effectively conduc...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | BERG MARK KRAMER ALLEN NICHOLAS |
description | Disclosed is a printed circuit board (PCB) layout for increasing the ability of the PCB to transfer heat away from a component mounted thereon. The locations of signal vias in the PCB are selected so as to define continuous pathways in a PCB heat sink layer. This allows heat to be effectively conducted away from thermal vias connected to heat sink layer, thereby preventing PCB-mounted components from overheating. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6574108B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6574108B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6574108B13</originalsourceid><addsrcrecordid>eNrjZNANTs1JTS7JLEtVCHB2UijLTFTIyU9OLMnMz1MoyVdIzctIzEtOVUjOz8_JzEvnYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxocFmpuYmhgYWTobGRCgBADGwKVQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Selective PCB via location to enhance cooling</title><source>esp@cenet</source><creator>BERG MARK ; KRAMER ALLEN NICHOLAS</creator><creatorcontrib>BERG MARK ; KRAMER ALLEN NICHOLAS</creatorcontrib><description>Disclosed is a printed circuit board (PCB) layout for increasing the ability of the PCB to transfer heat away from a component mounted thereon. The locations of signal vias in the PCB are selected so as to define continuous pathways in a PCB heat sink layer. This allows heat to be effectively conducted away from thermal vias connected to heat sink layer, thereby preventing PCB-mounted components from overheating.</description><edition>7</edition><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PHYSICS ; PRINTED CIRCUITS</subject><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20030603&DB=EPODOC&CC=US&NR=6574108B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20030603&DB=EPODOC&CC=US&NR=6574108B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BERG MARK</creatorcontrib><creatorcontrib>KRAMER ALLEN NICHOLAS</creatorcontrib><title>Selective PCB via location to enhance cooling</title><description>Disclosed is a printed circuit board (PCB) layout for increasing the ability of the PCB to transfer heat away from a component mounted thereon. The locations of signal vias in the PCB are selected so as to define continuous pathways in a PCB heat sink layer. This allows heat to be effectively conducted away from thermal vias connected to heat sink layer, thereby preventing PCB-mounted components from overheating.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PHYSICS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNANTs1JTS7JLEtVCHB2UijLTFTIyU9OLMnMz1MoyVdIzctIzEtOVUjOz8_JzEvnYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxocFmpuYmhgYWTobGRCgBADGwKVQ</recordid><startdate>20030603</startdate><enddate>20030603</enddate><creator>BERG MARK</creator><creator>KRAMER ALLEN NICHOLAS</creator><scope>EVB</scope></search><sort><creationdate>20030603</creationdate><title>Selective PCB via location to enhance cooling</title><author>BERG MARK ; KRAMER ALLEN NICHOLAS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6574108B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PHYSICS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>BERG MARK</creatorcontrib><creatorcontrib>KRAMER ALLEN NICHOLAS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BERG MARK</au><au>KRAMER ALLEN NICHOLAS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Selective PCB via location to enhance cooling</title><date>2003-06-03</date><risdate>2003</risdate><abstract>Disclosed is a printed circuit board (PCB) layout for increasing the ability of the PCB to transfer heat away from a component mounted thereon. The locations of signal vias in the PCB are selected so as to define continuous pathways in a PCB heat sink layer. This allows heat to be effectively conducted away from thermal vias connected to heat sink layer, thereby preventing PCB-mounted components from overheating.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US6574108B1 |
source | esp@cenet |
subjects | CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PHYSICS PRINTED CIRCUITS |
title | Selective PCB via location to enhance cooling |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-19T16%3A16%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BERG%20MARK&rft.date=2003-06-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6574108B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |