Method of manufacturing a transistor
A method of manufacturing a TFT (10) is disclosed comprising source (8) and drain (8'') electrodes joined by a semiconductor channel (6) formed from a semiconductor layer (4), a gate insulating layer (7) and a gate electrode (8'). The method comprising the steps of applying a foil (2)...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | A method of manufacturing a TFT (10) is disclosed comprising source (8) and drain (8'') electrodes joined by a semiconductor channel (6) formed from a semiconductor layer (4), a gate insulating layer (7) and a gate electrode (8'). The method comprising the steps of applying a foil (2) comprising a crystallization enhancing material (CEM) and depositing the semiconductor layer (4) over a supporting substrate (1); and heating the semiconductor layer (4) so as to crystallize the semiconductor layer (4) from regions exposed to the CEM of the foil (2). The method may further comprise the step of providing a patterned barrier layer (3) between the foil (2) and the semiconductor layer (4) wherein the semiconductor layer (4) is crystallized from regions exposed through vias in the barrier layer (3) to the CEM of the foil (2).Also disclosed is a TFT (10) manufactured by the same, and an active matrix device (20) comprising a row and column array of active elements (22) wherein each element (22) is associated with such a TFT (10) connected to corresponding row (24) and column (23) conductors. |
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