Wafer thickness compensation for interchip planarity
In a very dense integrated circuit package, including a carrier having a topography of projections with sloping sides for supporting individual semiconductor circuit chips with a conversely matching bottom surface topography to permit self-aligned positioning of the chip on the carrier, a method for...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | In a very dense integrated circuit package, including a carrier having a topography of projections with sloping sides for supporting individual semiconductor circuit chips with a conversely matching bottom surface topography to permit self-aligned positioning of the chip on the carrier, a method for compensating for variations in chip thickness by controlling the width of recesses in bottom surface topography so that alignment on the carrier projections will elevate thinner chips so that the device side of the chips are co-planar. |
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