Methods and circuits for testing programmable logic

Described is a test circuit that can be instantiated on a programmable logic device to perform at-speed functional tests of programmable resources, including internal memory and routing resources. The resources to be tested are configured to instantiate a counter circuit connected to the address terminals of a linear-feedback shift register (LFSR). LFSRs are cyclic, in the sense that when clocked repeatedly they go through a fixed sequence of states. Consequently, an LFSR that starts with a known set of data has a predictable set of data after a given number of clock periods. The LFSR is preset to a known count and clocked a known number of times. The resulting count is then compared with a reference. If the resulting count matches the reference, then all of the resources used to implement the test circuit, including the memory and routing resources used to implement the LFSR, are deemed fully functional at the selected clock speed. A test circuit employing an LFSR can be duplicated many times on a given device under test to consume (and therefore test) as many resources as possible.