Integrated circuit configuration for testing transistors, and a semiconductor wafer having such a circuit configuration

Circuit configurations for testing transistors are arranged in the scribe line between integrated circuits on a semiconductor wafer. In order to increase the number of testable transistors while consuming little surface area, the transistors are arranged in a matrix in at least two rows. The drain-source paths of the transistors in the first row are connected between pads, and their gate connections are connected to a common pad. The drain-source paths of the transistors in the second row are connected firstly to one of the pads, and are secondly jointly connected to a further pad. Their gate connections are likewise connected to a further pad. The matrix-like arrangement of the transistors can be extended by using additional rows.