Method and apparatus for extracting bridges from an integrated circuit layout

A bridge fault extractor. A computer-implemented method for performing fault extraction from an integrated circuit layout in a two-net analysis mode includes determining maximum critical areas from the layout for a maximum defect size of a set of defect sizes to be analyzed wherein each maximum critical area corresponds to a net-name pair. The maximum critical areas are then locally merged by net-name pair to determine an area of a union of maximum critical areas for each net-name pair. Critical areas for defect sizes smaller than the maximum defect size are determined from the maximum critical areas and locally merged by net-name pair to determine an area of a union of critical areas for each net-name pair for each smaller defect size. In a multi-net analysis mode, overlap rectangles are determined by net-name pair. The overlap rectangles are then used to calculate critical areas for two-net and multi-net bridges for each defect size in a set of defect sizes to be analyzed. In one aspect, similar to the two-net analysis mode, overlap rectangles are first determined for the maximum defect size and are resized for smaller defect sizes.