Method and apparatus for debugging an integrated circuit

Method and apparatus for debugging an integrated circuit

An integrated circuit having a normal mode for operating under normal operating conditions and a debug mode for operating to test and debug the integrated circuit. The integrated circuit includes a plurality of output pins that carry a first plurality of signals in the normal mode and carry a second...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MEHTA SHRENIK, GREENLEY DALE R, CARGNONI ROBERT A, MCFARLAND HAROLD L, FAVOR JOHN GREGORY, STILES DAVID R, VAN DYKE KORBIN S
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:An integrated circuit having a normal mode for operating under normal operating conditions and a debug mode for operating to test and debug the integrated circuit. The integrated circuit includes a plurality of output pins that carry a first plurality of signals in the normal mode and carry a second plurality of signals in the debug mode. In one embodiment, the integrated circuit embodies a microprocessor. The microprocessor may include logic circuitry for enabling the second plurality of signals to be output from a multiplexer to the output pins in response to a predetermined event, such as a hit in an associated memory unit.