Semiconductor memory device which receives write masking information

A semiconductor memory device and a method of operation in the semiconductor memory device. The memory device receives an external clock signal and includes an array of memory cells. The method of operation of the memory device includes receiving, during a first half of a clock cycle of the external clock signal, a first data value and a first mask bit. The first mask bit indicates whether to write the first data value to the array. The method further includes receiving, during a second half of the clock cycle of the external clock signal, a second data value and a second mask bit. The second mask bit indicates whether to write the second data value to the array.