Vertical deflection circuit, processor for vertical deflection, and CRT display

There is disclosed a vertical deflection circuit for use in a display device employing a CRT. The vertical deflection circuit has a DSP (digital signal processor) for producing a digital current signal during each main period. This digital current signal shows plural current values which increases in first equal increments from a different value during each main period. The digital current value is converted into an analog current signal by a D/A converter and then averaged by a low-pass filter. A vertical deflection current is produced based on the averaged analog current signal. Because plural different current values are averaged, the average value varies linearly. Accordingly, the vertical deflection current varies linearly with each main period.