Architecture, method (s) and circuitry for low power memories

Architecture, method (s) and circuitry for low power memories

A circuit comprising a plurality of groups of memory cells and a control circuit. The plurality of groups of memory cells may each (i) have a first and a second bitline and (ii) configured to read and write data to one or more of the plurality of groups of memory cells. The control circuit may be co...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: GEORGESCU BOGDAN I, MULHOLLAND SEAN B, ROSE DANNY L, GRADINARIU IULIAN C, FORD KEITH A, SILVER JOHN J
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:A circuit comprising a plurality of groups of memory cells and a control circuit. The plurality of groups of memory cells may each (i) have a first and a second bitline and (ii) configured to read and write data to one or more of the plurality of groups of memory cells. The control circuit may be configured to select an active group of the plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.