Method of forming an integrated circuit on a low loss substrate

Method of forming an integrated circuit on a low loss substrate

A method for manufacturing an integrated circuit structure is disclosed. The method includes providing a layer of porous silicon, and epitaxially growing a high resistivity layer on the layer of porous silicon. Devices are then formed on the high resistivity layer to produce the integrated circuit s...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: SCHEER ROBERT F, KALNITSKY ALEXANDER
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A method for manufacturing an integrated circuit structure is disclosed. The method includes providing a layer of porous silicon, and epitaxially growing a high resistivity layer on the layer of porous silicon. Devices are then formed on the high resistivity layer to produce the integrated circuit structure. The integrated circuit structure is attached to a silica substrate, such that the silica substrate is coupled to the devices. Further, surface contacts are provided on the structure. The layer of porous silicon is then removed.